Silicon-on-insulator (SOI) structures are widely used to form semiconductor packages due to the low cost of silicon materials, large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques. Within a conventional semiconductor package formed from SOI structure, parasitic coupling effects between devices (active or passive) are dominated by the parasitic coupling through the silicon handle layer of the SOI structure. The fact that the silicon's dielectric constant is much higher than the oxide's dielectric constant makes most field lines close through the silicon handle layer.
For the modern communication applications, a high degree of isolation between signal paths is highly desired. This in turn requires a low degree of parasitic coupling between devices. Other design constraints such as low insertion loss and high voltage swings result in large size devices. Such large size devices have large parasitic bottom capacitances that lead to poor isolation from other large size devices placed in close proximity.
Accordingly, there remains a need for improved semiconductor package designs with SOI structures to reduce parasitic coupling effects between devices within the semiconductor package. In addition, there is also a need to keep the size and cost of the final semiconductor package effective.